The present invention relates to a semiconductor integrated circuit, and more specifically, to a semiconductor integrated circuit capable of applying to a data reading circuit which reads out data stored in cells of a dynamic random access memory (DRAM).
An improvement of an integrated degree is one of the most important subjects for various large scale integrated circuits (LSI), which holds true for a DRAM without exception.
FIG. 1 shows a read circuit which reads bit line data of the DRAM to an external of a chip, and FIGS. 2A-2E show waveforms of reading operation. Hereunder, a symbol "*" is used as an indication of a negative logic, for example, in the case of the negative logic of a signal "D", there is represented as "*D".
In FIG. 1, the read circuit transmits data stored in a specified address memory cell in a plurality of memory cells 301 through a corresponding pair of bit lines BL1, *BL1; BL2, *BL2; . . . to a pair of data lines DQ and *DQ which are shared with all of bit lines corresponding to a row address. The data are transmitted from the pair of data lines DQ and *DQ through a pair of data lines D and *D to a pair of data lines R and *R, and finally outputted from an output circuit 312 as a read data D.sub.OUT.
The memory cells 301 corresponding to each column address are connected to a word line of each row address, and input ends of a differential amplifier circuit 302 are connected to each pair of bit lines of the memory cells 301. The differential amplifier circuit 302 is controlled by control signals SAP and *SAN with respect to an activated and inactivated conditions. When the signal SAP is "H" and the signal *SAN is "L", the circuit 302 is activated to amplify a fine potential difference between the corresponding bit lines. Output ends of the differential amplifier circuit are connected through a corresponding switch circuit 303 to a pair of data lines DQ and *DQ. A conduction or non-conduction of the switch circuit 303 is controlled by control signals CSL1, CSL2, . . . which are independently inputted, respectively. When the control signal CSL is "H", the switch circuit 303 becomes the conductive condition so as to cause the pair of bit lines to be electrically connected to the pair of data lines DQ, *DQ, thereby transmitting data of the pair of bit lines to the pair of data lines DQ and *DQ. Numeral 304 denotes an equalizing circuit, and the conductive or non-conductive condition is controlled by a control signal *E, in which the data lines DQ and *DQ are precharged to be a high-impedance condition when the control signal *E is "L". After a completion of the high-impedance condition, the switch circuit 303 is activated to be kept the pre charge condition or to be discharge condition corresponding to a level of the pair of bit lines, thereby transmitting the data of the pair of the bit lines to the pair of the data lines DQ and *DQ.
The data of the data lines DQ and *DQ are transmitted through a switch circuit 307 to the data lines D and *D. The switch circuit 307 is controlled of its conductive or non-conductive condition by the control signal S. Numeral 308 denotes an equalizing circuit of the data lines D and *D, and a conductive or non-conductive condition of transistors included in the equalizing circuit 308 is controlled by the control signal *E. Namely, when the control signal *E is "L", the transistors become the conductive condition to cause the data lines D and *D to be precharged. A transmission principle that the data of the data lines DQ and *DQ are transmitted to the data lines D and *D by means of the conduction of the switch circuit 307, is the same as the principle through the switch circuit 303. A differential amplifier 309 is connected to the data lines D and *D, an activated or non-activated condition of which is controlled by the control signals *E and QSE. When the control signal *E is "H" and the control signal QSE is "H", the differential amplifier 309 is activated so as to amplify the potential difference of the data lines D and *D.
The data of the data lines D and *D are transmitted to data lines R and *R each through potential transmission circuits 310 and 311 which are provided corresponding to each line, respectively. The conductive or non-conductive condition of the potential transmission circuit 310 and 311 is controlled by the control signal *E. When the control signal *E is "H", a potential of the each of data lines D and *D is transmitted to each of data lines R and *R. An output circuit 312 outputs the data based on the potential of the data lines R and *R as read-out data D.sub.OUT toward external of the chip.
Numerals 305 and 306 are write control circuits, which are respectively comprised of inverters having an ON/OFF condition to be controlled by write enable signals WE and *WE. Write data WD and *WD are inputted through the inverters into the data lines DQ and *DQ, and are written into the memory cell 301 selected.
Next, operation of the read circuit will be described with reference to FIG. 1 and also FIGS. 2A-AE. In these figures, there is described the case where, after the data of the bit lines BL1 and *BL1 are read in a region I, an address is changed over in a region II so as to read the data of the bit lines BL2 and *BL2.
A word line WL first rises up so as to transmit data in each of the memory cells 301 to the bit lines BL1, *BL1; BL2, *BL2. After a fine potential difference occurs between the bit lines BL1-*BL1 and between the bit lines BL2-*BL2, the signal *SAN is reduced from the bit line potential to the ground potential, and the signal SAP is increased from the bit line potential to a predetermined potential, thereby activating the differential amplifier 302 to amplify the potential difference of the bit lines (in a time period T.sub.a in FIGS. 2A-2E).
Next, the signal *E rises up to control equalizing circuits 304 and 308 which cause the data lines DQ, *DQ, D, *D, R and *R to keep the power source potential so as to be a high-impedance condition. After that, the control signals CSL1 and S rise up for controlling the switch 303 (connecting the bit lines BL1 and *BL1 with the data lines DQ and *DQ) and the switch 307 connecting the data lines DQ and *DQ with the data lines D and *D), respectively, so as to cause the switches 303 and 307 to be non-activated, thereby transmitting charges of the bit lines to both of the data lines DQ, *DQ and D, *D. After that, the signal S rises to cause the switch 307 to be non-activated, and at the same time, the signal QSE rises to activate the differential amplifier circuit 309 of the data lines D and *D, thereby amplifying the fine potential difference of the data lines D and *D (refer to the time periods T.sub.b, T.sub.c and T.sub.d of FIGS. 2A-2E). Amplified data of the data lines D and *D are supplied to the transmission circuit 310 and 311 as described above, and output data of the circuits 310 and 311 are transmitted through the data lines R and *R and the output circuit 312 as the output data D.sub.OUT from the chip to the external.
Next, when the address inputted to the chip changes and this change is received by an in-chip control circuit, the signal CSL1, which connects the bit lines BL1 and *BL1 with the data lines DQ and *DQ, rises to cause the switch 303 to be non-activated. At substantially the same time, the control signal *E and S trail to increase the data lines DQ, *DQ; D, *D; R and *R up to an "H" level. When the potential of each of the data lines rises to the same potential, the control signal *E is changed to the "H" level so as to turn off the charging circuits 304 and 308 and the transmission circuits 310 and 311. At the same time, the control signal CSL2 rises up to cause the switch 303 to be activated, thereby transmitting the data of the bit lines BL2 and *BL2 to the data lines DQ and *DQ. The potential difference between the data lines DQ and *DQ is transmitted through the switch 307 to the data lines D and *D, and at the time point where the fine potential difference occurs between the data lines D and *D, the control signals S and QSE rise to cause the differential amplifier circuit 309 to be activated, thereby amplifying the potential difference between the data lines D and *D. The potential is transmitted through the transmission circuits 310 and 311 to the data lines R and *R, and further transmitted to the output circuit 312 so as to output the chip output D.sub.OUT.
However, in such a DRAM circuit described above, the problem resides in that the improvement of the integrated degree cause access operation to be reduced. The cause of the above problem relates to a securement of the equalizing time in the data lines DQ and *DQ.
Namely, such data lines DQ and *DQ have a load capacitance usually larger than that of the data lines D and *D, and this condition can be understood by FIGS. 2A-2E. When the integrated degree improves to increase the memory capacitance, the data lines DQ and *DQ are connected to a large number of the bit lines according to the increase of the memory capacitance, thereby increasing the load capacitance. Namely, the data lines DQ and *DQ have the large time constant. Therefore, for sufficiently equalizing the data lines DQ and *DQ to secure the data read, the time to secure reading (the period to cause the equalizing control signal E to be "L") should be long corresponding to the securement, thereby resulting the decrease of the operational speed caused by the improvement of the integrated degree.
Also, high-speed operation becomes one of the most important matter with the high integrated degree, the operational speed of the LSI device around the memory has been increasing steadily. Accordingly, with this improvement, high speed operation with respect to the access speed of the DRAM is required more and more.